Publication details
SystemVerilog verification of VHDL design
| Basic information | |
|---|---|
| Original title: | SystemVerilog verification of VHDL design |
| Authors: | David Šafránek, Petr Kobierský, Viktor Puš, Tom Málek |
| Further information | |
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| Citation: | ŠAFRÁNEK, David, Petr KOBIERSKÝ, Viktor PUŠ and Tom MÁLEK.
SystemVerilog verification of VHDL design. CESNET, z.s.p.o.
Praha: CESNET, z.s.p.o., 2007. CESNET Technical Reports.Export BibTeX @misc{752397, author = {Šafránek, David and Kobierský, Petr and Puš, Viktor and Málek, Tom}, address = {Praha}, edition = {CESNET, z.s.p.o.}, language = {eng}, location = {Praha}, publisher = {CESNET, z.s.p.o.}, title = {SystemVerilog verification of VHDL design}, url = {http://www.cesnet.cz/doc/techzpravy/2007/systemverilog  -vhdl-verification/},year = {2007} } |
| Original language: | English |
| Field: | Informatics |
| WWW: |  http://www.cesnet.cz/doc/techzpravy/2007/systemverilog-vhdl-verification/ |
| Type: | R&D Presentation |
This document describes digital design verification methods used in Liberouter project. Because of the high effort required for employing exhaustive formal verification method of model checking on large and rapidly developed designs, we have explored possibilities of supplementing this method by a relatively easily practicable simulation method based on the notion of testbenches. In particular, we report on SystemVerilog framework for automated and manageable tests and we highlight the most interesting aspects of both mentioned verification methods. Finally, we evaluate the SystemVerilog simulation on complex Internal Bus design. Very good results of SystemVerilog simulation encourage use of this approach to all critical and complex designs. We also state some preliminary ideas of how to combine both verification methods together to gain maximum of their features.
