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Publication details

Verification of COMBO6 VHDL Design

Further information
Citation:	KRATOCHVÍLA, Tomáš - ŘEHÁK, Vojtěch - ŠIMEČEK, Pavel. Verification of COMBO6 VHDL Design. Praha : CESNET, z.s.p.o., 2003. CESNET Technical Report No. 17/2003. WWW
Original language:	English
Field:	Informatika
WWW:	http://www.cesnet.cz/doc/techzpravy/2003/translationver/
Type:	R&D Presentation
Keywords:	Liberouter; Combo6; formal verification; hardware verification; model checking; Cadence SMV; LeonardoSpectrum

This technical report presents current results and experiences of the formal verification of VHDL design of Combo6 hardware accelerator card. Information about formal verification itself is enriched by description of transformation from VHDL to the Cadence SMV specification language and the system of assertions established as a compact way of communication with VHDL designers.

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