Publication details
Hardware Router's Lookup Machine and its Formal Verification
| Basic information | |
|---|---|
| Original title: | Hardware Router's Lookup Machine and its Formal Verification |
| Authors: | David Antoš, Vojtěch Řehák, Jan Kořenek |
| Further information | |
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| Citation: | ANTOŠ, David  - ŘEHÁK, Vojtěch - KOŘENEK, Jan. Hardware Router's Lookup Machine and its Formal Verification. In ICN'2004 Conference Proceedings. Gosier, Guadeloupe, French Caribbean : University of Haute Alsace, Colmar, France, 2004. ISBN 0-86341-325-0, pp. 1002-1007. 29.2.2004, Gosier, Guadeloupe. |
| Original language: | English |
| Field: | Informatika |
| WWW: |  http://conf.uha.fr/ICN2004.html |
| Type: | Article in Proceedings |
| Keywords: | IPv6 routing; FPGA; formal verification; Liberouter |
This article describes the design of the lookup machine implemented in hardware accelerator COMBO6 for IPv6 and IPv4 packet routing. The lookup machine is a single instruction machine using Content Addressable and Static Memories and the operations are performed by Field Programmable Gate Arrays. The design of the lookup machine is difficult to be proven correct by conventional methods, therefore model checking as a method of formal verification was employed and this case is explained in detail. In the last part, the article sums up software support needed to make behavior of the accelerator equivalent to the host computer.
Related projects:
- Automated Verification of Parallel and Distributed Systems
- Large-scale International Ipv6 Testbed
- Non-sequential Models of Computing -- Quantum and Concurrent Distributed Models of Computing
