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Packet Filtering for FPGA-Based Routing Accelerator

Basic information
Original title:Packet Filtering for FPGA-Based Routing Accelerator
Authors:David Antoš, Vojtěch Řehák, Petr Holub
Further information
Citation:ANTOŠ, David, Vojtěch ŘEHÁK and Petr HOLUB. Packet Filtering for FPGA-Based Routing Accelerator. In CESNET Conference 2006 Proceedings. Prague: CESNET, z. s. p. o., 2006. p. 161--173, 13 pp. ISBN 80-239-6533-6.Export BibTeX
@inproceedings{630886,
author = {Antoš, David and Řehák, Vojtěch and Holub, Petr},
address = {Prague},
booktitle = {CESNET Conference 2006 Proceedings},
keywords = {packet filtering; hardware accelerated routing; filtring rules transformation; filtering decision diagram; binary decision diagram},
language = {eng},
location = {Prague},
isbn = {80-239-6533-6},
pages = {161--173},
publisher = {CESNET, z. s. p. o.},
title = {Packet Filtering for FPGA-Based Routing Accelerator},
url = {http://www.ces.net/conference06/},
year = {2006}
}
Original language:English
Field:Computer hardware and software
WWW:link to a new windowhttp://www.ces.net/conference06/
Type:Article in Proceedings
Keywords:packet filtering; hardware accelerated routing; filtring rules transformation; filtering decision diagram; binary decision diagram

In this paper, we present a novel approach for Binary Decision Diagram based semantically extended representation of packet filters called Filter Decision Diagrams (FDD), used for efficient filter processing and lookup in a hardware accelerator that uses a lookup engine employing CAM and comparison instructions kept in SRAM. We present the most important operations for FDDs and also give some complexity estimate. We also analyze and compare expressing power of the most commonly available packet filters.

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