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Revisiting Resistance Speeds Up I/O Efficient LTL Model Checking

Basic information
Original title:Revisiting Resistance Speeds Up I/O Efficient LTL Model Checking
Authors:Jiří Barnat, Luboš Brim, Pavel Šimeček, Michael Weber
Further information
Citation:BARNAT, Jiří - BRIM, Luboš - ŠIMEČEK, Pavel - WEBER, Michael. Revisiting Resistance Speeds Up I/O Efficient LTL Model Checking. In Tools and Algorithms for the Construction and Analysis of Systems. Berlin, Heidelberg : Springer-Verlag, 2008. ISBN 978-3-540-78799-0, pp. 48-62. 2008, Budapest, Hungary.
Original language:English
Field:Informatika
Type:Article in Proceedings
Keywords:I/O efficient; accepting cycle detection; revisiting resistance

Revisiting resistance graph algorithms are those, whose correctness is not vulnerable to repeated edge exploration. Revisiting resistant I/O efficient graph algorithms exhibit considerable speed-up in practice in comparison to non-revisiting resistant algorithms. In the paper we present a new revisiting resistant I/O efficient LTL model checking algorithm. We analyze its theoretical I/O complexity and we experimentally compare its performance to already existing I/O efficient LTL model checking algorithms.

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