doc. RNDr. Vojtěch Řehák, Ph.D.
proděkan pro studijní programy a internacionalizaci Fakulty informatiky
kancelář: C436
Botanická 554/68a
602 00 Brno
telefon: | 549 49 4687 |
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e‑mail: |
sociální a akademické sítě: |
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Počet publikací: 66
2009
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Almost Linear Büchi Automata
Proceedings 16th International Workshop on Expressiveness in Concurrency 2009 (EXPRESS'09), rok: 2009
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On Decidability of LTL Model Checking for Process Rewrite Systems
Acta informatica, rok: 2009, ročník: 46, vydání: 1
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On Decidability of LTL+Past Model Checking for Process Rewrite Systems
Joint Proceedings of the 8th, 9th, and 10th International Workshops on Verification of Infinite-State Systems (INFINITY 2006, 2007, 2008), rok: 2009
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Reachability is decidable for weakly extended process rewrite systems
Information and Computation, rok: 2009, ročník: 207, vydání: 6
2008
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Petri Nets Are Less Expressive Than State-Extended PA
Theoretical Computer Science, rok: 2008, ročník: 394, vydání: 1-2
2007
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Formalisms and Tools for Design and Specification of Network Protocols
Rok: 2007, druh: Prezentace v oblasti VaV (AV tvorba, WEB aplikace apod.)
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On Decidability of LTL+Past Model Checking for Process Rewrite Systems
Rok: 2007, druh: Další prezentace na konferencích
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Verifying VHDL Designs with Multiple Clocks in SMV
Formal Methods Applications and Technology, 11th International Workshop on Formal Methods for Industrial Critical Systems, FMICS 2006, and 5th International Workshop on Parallel and Distributed Methods in Verification, PDMC 2006, rok: 2007
2006
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Formal Verification of a FIFO Component in Design of Network Monitoring Hardware
10 years of CESNET - CESNET CONFERENCE 2006, rok: 2006
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Formal Verification of the CRC Algorithm Properties
Proceedings of 2nd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS 2006), rok: 2006