Techniques for automatic verification and validation of software nad hardware systems
- Project Identification
- Project Period
- 1/2005 - 12/2009
- Investor / Pogramme / Project type
- Academy of Sciences of the Czech Republic
- MU Faculty or unit
- Faculty of Informatics
- Computer aided and automatic verication, theory and technology of modellingof large systems, methodology of software engineering, embedded systems, parallel and distributed systems, real time systems.
The main objective of the project is to create a theoretical and methodological base for computer-aided and automatic verification and validation of large software and hardware systems. The project aims to support the development of methodologies, technologies and tools of software engineering in automatic and computer-aided verification. The project is to contribute to the research into new technologies for a realistic modelling of large systems, including real-time systems and probabilistic systems, especially with respect to their safety. The aim is to design effective implementations of these models as well as efficient verification technologies based on such models. The project will focus on embedded, distributed and parallel systems. Taking into consideration the complexity of verification processes, the aim is to design methodologies that will make the maximum possible use of new information technologies, such as parallel and distributed computing and hierarchical memories.
Total number of publications: 94