doc. RNDr. Vojtěch Řehák, Ph.D.
proděkan pro studijní programy a internacionalizaci Fakulty informatiky
kancelář: A408
Botanická 554/68a
602 00 Brno
| telefon: | 549 49 4687 |
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| e‑mail: |
| sociální a akademické sítě: |
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Počet publikací: 69
2007
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Verifying VHDL Designs with Multiple Clocks in SMV
Formal Methods Applications and Technology, 11th International Workshop on Formal Methods for Industrial Critical Systems, FMICS 2006, and 5th International Workshop on Parallel and Distributed Methods in Verification, PDMC 2006, rok: 2007
2006
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Formal Verification of a FIFO Component in Design of Network Monitoring Hardware
10 years of CESNET - CESNET CONFERENCE 2006, rok: 2006
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Formal Verification of the CRC Algorithm Properties
Proceedings of 2nd Doctoral Workshop on Mathematical and Engineering Methods in Computer Science (MEMICS 2006), rok: 2006
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On Decidability of LTL Model Checking for Process Rewrite Systems
FSTTCS 2006: 26th International Conference on Foundations of Software Technology and Theoretical Computer Science, 26th International Conference, Kolkata, India, December 13-15, 2006, Proceedings, rok: 2006
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On Decidability of LTL Model Checking for Weakly Extended Process Rewrite Systems
Rok: 2006, druh: Prezentace v oblasti VaV (AV tvorba, WEB aplikace apod.)
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Packet Filtering for FPGA-Based Routing Accelerator
CESNET Conference 2006 Proceedings, rok: 2006
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Refining Undecidability Border of Weak Bisimilarity.
Proceedings of the 7th International Workshop on Verification of Infinite-State Systems (INFINITY'05), rok: 2006
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Routing and Level 2 Addressing in a Hardware Accelerator for Network Applications
ICT 2006, 13th International Conference on Telecommunications, rok: 2006
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Routing, L2 Addressing, and Packet Filtering in a Hardware Engine
Proceedings of MEMICS 2006, rok: 2006
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Weakly Extended Process Rewrite Systems
Rok: 2006, druh: Další prezentace na konferencích